71. G. S. Lin and J. B. Kuo, “Fringing-Induced Slim-Channel-Effect (FINCE) Associated Capacitance Behavior off Nanometer FD SOI NMOS Devices Playing with Mesa-Isolation Thru three-dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Progression regarding Bootstrap Approaches to Lowest-Current CMOS Digital VLSI Circuits for SOC Programs” , IWSOC , Banff, Canada ,
P. Yang, “Entrance Misalignment Feeling Relevant Capacitance Decisions away from an excellent 100nm DG FD SOI NMOS Product with letter+/p+ Poly Most useful/Base Entrance” , ICSICT , Beijing, Asia
73. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Productive CMOS High-Load Rider Routine towards the Complementary Adiabatic/Bootstrap (CAB) Way of Lowest-Strength TFT-Liquid crystal display Program Applications” , ISCAS , Kobe, The japanese ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Trend off 100nm FD SOI CMOS Products which have HfO2 High-k Entrance Dielectric Given Vertical and you can Fringing Displacement Effects” , HKEDSSC , Hong-kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Related Capacitance Choices out-of a great 100nm DG SOI MOS Devices that have N+/p+ Top/Base Entrance” , HKEDSSC , Hong kong ,
76. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Effective CMOS High-Load Driver Routine toward Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Stamina TFT-Liquid crystal display System Apps” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you can J. B. Kuo, “Good 0.8V CMOS TSPC Adiabatic DCVS Reason Circuit with the Bootstrap Techniques for Reduced-Stamina VLSI” , ICECS , Israel ,
B. Kuo, “A manuscript 0
80. J. B. Kuo and you can H. P. Chen, “A minimal-Voltage CMOS Weight Driver into Adiabatic and you may Bootstrap Approaches for Low-Stamina Program Programs” , MWSCAS , Hiroshima, The japanese ,
83. Yards. T. Lin, Elizabeth. C. Sunlight, and J. B. Kuo, “Asymmetric Entrance Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Products Given Fringing Electronic Field effect” , Electron Equipment and Thing Symposium ,
84. J. B. Kuo, Elizabeth. C. Sun, and Meters. T. Lin, “Analysis out of Gate Misalignment Effect on this new Endurance Voltage regarding Double-Gate (DG) Ultrathin FD SOI NMOS Gadgets Using a compact Model Provided Fringing Electric Field-effect” , IEEE Electron Devices getting Microwave oven and you will Optoelectronic Software ,
86. E. Shen and you can J. 8V BP-DTMOS Content Addressable Memories Phone Routine Based on SOI-DTMOS Process” , IEEE Meeting towards Electron Gadgets and Solid state Circuits , Hong-kong ,
87. P. C. Chen and you can J. B. Kuo, “ic Reasoning Routine Using an immediate Bootstrap (DB) Way of Reduced-voltage CMOS VLSI” , All over the world Symposium into the Circuits and Assistance ,
89. J. B. Kuo and you will S. C. Lin, “Compact Dysfunction Model for PD SOI NMOS Gadgets Offered BJT/MOS Impact Ionization having Spice Circuits Simulation” , IEDMS , Taipei ,
ninety. J. B. Kuo and you will S. C. Lin, “Lightweight LDD/FD SOI CMOS Equipment Model Considering Opportunity Transport and you will Worry about Heating having Spice Routine Simulator” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B. Kuo, “Fringing-Created Hindrance Decreasing (FIBL) Outcomes of 100nm FD SOI NMOS Gadgets with high Permittivity Gate Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,
92. J. B. Kuo and S. C. Lin, “The newest Fringing Electric Field effect with the Small-Station Impact Tolerance Voltage regarding FD SOI NMOS Devices which have LDD/Sidewall Oxide Spacer Construction” , Hong kong Electron Gizmos Conference ,
93. C. L. Yang and J. B. Kuo, “High-Temperatures Quasi-Saturation Make of Large-Current DMOS Power Equipment” , Hong-kong Electron Gizmos Fulfilling ,
94. Age. Shen and you may J. B https://kissbrides.com/latvian-brides/. Kuo, “0.8V CMOS Content-Addressable-Memories (CAM) Mobile Ciurcuit that have an easy Level-Compare Effectiveness Playing with Bulk PMOS Dynamic-Threshold (BP-DTMOS) Method According to Standard CMOS Technical to own Reasonable-Current VLSI Options” , All over the world Symposium with the Circuits and you will Systems (ISCAS) Process , Arizona ,